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| features q 55ns maximum address access time, single-event upset less than 1.0e-10 errors//bit day (-55 o c to 125+ o c) q asynchronous operation for compatibility with industry- standard 8k x 8 sram q ttl-compatible input and output levels q three-state bidirectional data bus q low operating and standby current q full military operating temperature range, -55 o c to 125+ o c, screened to specific test methods listed in table i mil-std- 883 method 5004 for class s or class b q radiation-hardened process and design; total dose irradiation testing to mil-std-883 method 1019 - total-dose: 1.0e6 rads(si) - dose rate upset: 1.0e9 rads (si)/sec - dose rate survival: 1.0e12 rads (si)/sec - single-event upset: <1.0e-10 errors/bit-day q industry standard (jedec) 64k sram pinout q packaging options: - 28-pin 100-mil center dip (.600 x 1.2) - 28-pin 50-mil center flatpack (.700 x .75) q 5-volt operation q post-radiation ac/dc performance characteristics guaranteed by mil-std-883 method 1019 testing at 1.0e6 rads(si) introduction the ut67164 sram is a high performance, asynchronous, radiation-hardened, 8k x 8 random access memory conforming to industry-standard fit, form, and function. the ut67164 sram features fully static operation requiring no external clocks or timing strobes. utmc designed and implemented the ut67164 using an advanced radiation- hardened twin-well cmos process. advanced cmos processing along with a device enable/disable function result in a high performance, power-saving sram. the combination of radiation-hardness, fast access time, and low power consumption make ut67164 ideal for high-speed systems designed for operation in radiation environments. input drivers 256 x 256 memory array column i/o figure 1. sram block diagram input drivers a(4:0) input drivers a(12:5) row decoders output enable e2 w g e1 chip enable output drivers data write circuit data read circuit dq(7:0) column decoders write enable standard products ut67164 radiation-hardened 8k x 8 sram -- seu hard data sheet january 2002
2 pin names device operation the ut67164 has four control inputs called enable 1 ( e1 ), enable 2 (e2), write enable ( w ), and output enable ( g ); 13 address inputs, a(12:0); and eight bidirectional data lines, dq(7:0). e1 and e2 are device enable inputs that control device selection, active, and standby modes. asserting both e1 and e2 enables the device, causes i dd to rise to its active value, and decodes the 13 address inputs to select one of 8,192 words in the memory. w controls read and write operations. during a read cycle, g must be asserted to enable the outputs. table 1. device operation truth table notes: 1. ?x? is defined as a ?don?t care? condition. 2. device active; outputs disabled. read cycle a combination of w greater than v ih (min), e1 less than v il (max), and e2 greater than v ih (min) defines a read cycle. read access time is measured from the latter of device enable, output enable, or valid address to valid data output. read cycle 1, the address access read in figure 3a, is initiated by a change in address inputs while the chip is enabled with g asserted and w deasserted. valid data appears on data outputs dq(7:0) after the specified t avqv is satisfied. outputs remain active throughout the entire cycle. as long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (t avav ). figure 3b shows read cycle 2, the chip enable-controlled access. for this cycle, g remains asserted, w remains deasserted, and the addresses remain stable for the entire cycle. after the specified t etqv is satisfied, the eight-bit word addressed by a(12:0) is accessed and appears at the data outputs dq(7:0). figure 3c shows read cycle 3, the output enable-controlled access. for this cycle, e1 and e2 are asserted, w is deasserted, and the addresses are stable before g is enabled. read access time is t glqv unless t avqv or t etqv have not been satisfied. a(12:0) address w write dq(7:0) data input/output g output enable e1 enable 1 v dd power e2 1 enable 2 v ss ground 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 figure 2. sram pinout nc a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 vss vdd w e2 a8 a9 a11 g a10 e1 dq7 dq6 dq5 dq4 dq3 g w e1 e2 i/o mode mode x 1 x x 0 3-state standby x x 1 x 3-state standby x 0 0 1 data in write 1 1 0 1 3-state read 2 0 1 0 1 data out read 3 write cycle a combination of w less than v il (max), e1 less than v il (max), and e2 greater than v ih (min) defines a write cycle. the state of g is a ?don?t care? for a write cycle. the outputs are placed in the high-impedance state when either g is greater than v ih (min), or when w is less than v il (max). write cycle 1, the write enable-controlled access shown in figure 4a, is defined by a write terminated by w going high, with e1 and e2 still active. the write pulse width is defined by t wlwh when the write is initiated by w , and by t etwh when the write is initiated by the latter of e1 or e2. unless the outputs have been previously placed in the high-impedance state by g , the user must wait t wlqz before applying data to the eight bidirectional pins dq(7:0) to avoid bus contention. write cycle 2, the chip enable-controlled access shown in figure 4b, is defined by a write terminated by the latter of e1 or e2 going inactive. the write pulse width is defined by t wlef when the write is initiated by w , and by t etef when the write is initiated by the latter of e1 or e2 going active. for the w initiated write, unless the outputs have been previously placed in the high-impedance state by g , the user must wait t wlqz before applying data to the eight bidirectional pins dq(7:0) to avoid bus contention. radiation hardness the ut67164 sram incorporates special design and layout features which allow operation in high-level radiation environments. table 2. radiation hardness design specifications 1 notes: 1. the sram will not latchup during radiation exposure under recommended operating conditions. 2. 90% adam?s worst case spectrum (-55 o c to 125+ o c). total dose 1.0e6 rads(si) dose rate upset 1.0e9 rads(si)/s 20ns pulse dose rate survival 1.0e12 rads(si)/s 20ns pulse single-event upset 1.0e-10 errors/bit day 2 neutron fluencs 3.0e14 n/cm 2 table 3. seu versus temperature s e u e r r o r s / b i t - d a y 10 -4 10 -6 10 -8 10 -10 10 -10 10 -13 10 -11 10 -12 10 -13 10 -14 10 -16 -55 -35 -15 5 25 45 65 85 105 125 temperature ( o c) 4 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. e xposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. test per mil-std-883, method 1012. recommended operating conditions symbol parameter limits v dd dc supply voltage -0.5 to 7.0v v i/o voltage on any pin -0.5 to v dd + 0.5 t stg storage temperature -65 to +150 c p d maximum power dissipation 1.0w t j maximum junction temperature +150 c q jc thermal resistance, junction-to-case 2 10 c/w i lu latchup immunity +/-150ma i i dc input current +/- 10 ma symbol parameter limits units v dd positive supply voltage 4.5 to 5.5v v t c case temperature range -55 to +125 c o c v in dc input voltage 0v to v dd v 5 dc electrical characteristics (pre/post-radiation)* (v dd = 5.0v10%; -55 c 8 ac characteristics write cycle (post-radiation)* (v dd = 5.0v 10%: -55 c < t c < +125 c) notes : * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019at 1.0e6 rads(si). symbol parameter 67164-85 min max 67164-70 min max 67164-55 min max unit t avav write cycle time 85 70 55 ns t etwh device enable to end of write 65 60 50 ns t avet address setup time for write ( e1 or e2 - controlled) 0 0 0 ns t avwl address setup time for write ( w - controlled) 0 0 0 ns t wlwh write pulse width 50 35 35 ns t whax address hold time for write ( w - controlled) 0 0 0 ns t efax address hold time for device enable ( e1 or e2 - controlled) 0 0 0 ns t wlqz w - controlled three-state time 15 15 15 ns t whqx w - controlled output enable time 0 0 0 ns t etef device enable pulse width ( e1 or e2 - controlled) 65 60 55 ns t dvwh data setup time 50 35 35 ns t whdx data hold time 0 0 0 ns t wlef device enable controlled write pulse width 65 60 50 ns t dvef data setup time 50 35 35 ns t efdx data hold time 0 0 0 ns 9 assumptions: 1. g < v il (max). if g > v ih (min) then q(7:0) will be in three-state for the entire cycle. w e1 t avwl figure 4a. sram write cycle 1: w - controlled access a(12:0) q(7:0) e2 t avav 2 d(7:0) applied data t dvwh t whdx t etwh t wlwh t whax t whqx t wlqz 10 t efdx 5 assumptions & notes: 1. g < v il (max). if g > v ih (min) then q(7:0) will be in three-state for the entire cycle. 2. either e1 /e2 scenario above can occur. 3. if e1 or e2 is asserted simultaneously wih or after the w low transition, the outputs will remain in a high-impedance state. 4. t wlef = t etwh. 5. t efdx = t whdx. 6. t dvef = t dvwh a(12:0) figure 4b. sram write cycle 2: enable - controlled access w e2 e1 d(7:0) applied data e1 e2 q(7:0) t wlqz t etef t wlef 4 t dvef 6 t avav t avet t avet t etef t efax t efax t etqx 3 11 data retention characteristics (post-radiation) (t c = 25 c) notes: * post-radiation performance guaranteed at 25 o c per mil-std-883 method 1019 at 1.0e6 rads(si). 1. v lc = 0.2v, v hc = v dd -0.2v, e1 > v hc, e2 > v hc symbol parameter minimum maximum v dd @ unit 2.0v 3.0v v dr v dd for data retention 2.5 -- v i dddr 1 data retention current -- 75 90 m a t efr 1 chip deselect to data retention time 0 ns t r 1 operation recovery time t avav ns v dd e1 data retention mode t r 4.5v 4.5v v dr > 2.5v figure 5. low v dd data retention waveform t efr v dr v ih v ih notes: 1. 30pf including scope probe and test socket. 2. measurement of data output occurs at the low to high or high to low transition mid-point 90% figure 6. ac test loads and input waveforms input pulses 10% < 5ns < 5ns 5.0v 30pf 90% 10% 174 ohms 446 ohms 12 figure 7. 28-pin ceramic dip package notes: 1. seal ring to be electrically isolated. 2. all exposed metalized areas to be plated per mil-prf-38535. 3. ceramic to be opaque. 4. dimension letters refer to mil-std-1835. d 1.40 0.020 pin no. 1 id. s1 0.005 min. s2 0.005 min. e 0.595 0.015 e1 0.600 + 0.020 - 0.010 c 0.010 + 0.002 - 0.001 a 0.175 max. l1 0.150 min. l 0.200 0.125 e 0.100 b 0.018 0.002 q 0.060 0.015 13 notes: 1. lid is electrically isolated. 2. all exposed metalized areas are plated per mil-prf-38535. 3. ceramic is opaque. 4. dimension letters refer to mil-std-1835 figure 8. 28-lead 50-mil center flatpack (0.700 x 0.75) 14 ordering information 64k sram: ut 67164 * ** - * * * * * none lead finish: (a) = solder (c) = gold (x) = optional screening: (p) = prototype (contact factory for availability) (c) = military temperature (contact factory for availability) package type: (p) = 28-pin dip (w) = 28-pin flatpack access time: (55) = 55ns access time (70) = 70ns access time (85) = 85ns access time utmc core part number notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (g old). 3. 85 ns not available for prototype flow devices. 4. mil temp range flow per utmc?s manufacturing flows document. devices are tested at -55c, room temp, and 125c. radiation neither tested nor guaranteed. 5. prototypes are produced to utmc?s prototype flow, and tested at 25c only. lead finish is at utmc?s option. radiation is neither tested nor guaranteed. 15 64k sram: smd lead finish: (a) = solder (c) = gold (x) = option case outline: (n) = 28-pin fp (x) = 28-pin dip class designator: (b) = qml class q (s) = qml class v device type (35) = 85ns access time (36) = 75ns access time (37) = 55ns access time (contact factory for availability) drawing number: 38294 total dose: (h) = 1e6 rads(si) (r) = 5e5 rads(si) federal stock class designator: no options 5962 notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering then the part marking is at the factory?s option and will match the lead finish ?a? (sol der) or ?c? (gold). |
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